Physically aware DFT: Is it worth all the heavy lifting?

DFT tools that look at physical effects are already available from EDA tool providers. For example there are small delay defect (SDD) tools that try to take into account interconnect defects such as partial opens as well as process variations by looking at a node´s slack. And there are bridging fault tools that look for shorts between conductive structures. However, both of these tools are known to have extremely long CPU run times and produce very large pattern sets. Also, silicon providers seem to be caught in a catch-22 with the tool vendors over these issues. EDA companies want silicon test data and physical failure analysis showing that their tools are effective before they invest any effort in improving the run time and pattern size issues of existing tools but often the silicon providers can´t use these tools to collect this data until the tools have first been improved. If this wasn´t enough of a problem, some silicon providers have found that the patterns produced by these commercial physically aware tools are no more effective at catching defects than regular stuck-at and transition delay fault patterns. Are we heading in the right direction by developing these physically aware tools and are the issues described above just growing pains? Or should we just ditch the effort - stuck-at and standard transition fault are good enough?