Title :
A Harmonic-Free and Fast-Locking Delay-Locked Loop Adopting a Resettable Delay Line
Author :
Huang, Kai ; Cai, Zhikuang ; Yang, Jun
Author_Institution :
ASIC Center, Southeast Univ., Nanjing, China
Abstract :
An all digital delay-locked loop (ADDLL) with "reset in every step" (RES) delay line is developed in order to reduce the locking time. Due to the novel resettable mechanism of delay line, the DLL has the property of fast-locking and harmonic-free. The locking time can be reduced to N+1, where N is the bits\´ number of the control code for a delay line. According to the simulation result in SMIC 180nm CMOS technology, the proposed delay-locked loop (DLL) can cover the operating range from 50 to 250MHz.
Keywords :
CMOS integrated circuits; delay lock loops; CMOS technology; all digital delay-locked loop; delay-locked loop; frequency 50 MHz to 250 MHz; harmonic-free-fast-locking delay-locked loop; reset in every step; resettable delay line; Added delay; Application specific integrated circuits; CMOS technology; Circuit simulation; Clocks; Delay effects; Delay lines; Mechanical factors; Research and development; Timing; delay line; delay-locked loop; fast-locking; harmonic-free;
Conference_Titel :
Computer Research and Development, 2010 Second International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-0-7695-4043-6
DOI :
10.1109/ICCRD.2010.176
