Compensator Design for Adaptive Voltage Positioning (AVP) for Multiphase VRMs

In an AVP scheme, feedback compensation design is crucial to achieve a desirable constant converter output impedance while maintaining converter stability. The model proposed and the analysis given provides insightful view of the interaction of the two performances. Depending on the relative location of the noise-suppressing compensation pole with respect to the capacitor ESR-zero frequency, the performance of output impedance and stability margin can be vary a great deal. If the two frequencies are too close to each other, the stability margins get small, and Z_OC exhibits a spike/dip at the ESR-zero frequency. This happens in a realistic case, when ceramics capacitors are used and switching frequency is set high. This conclusion is verified in a SIMPLIS simulation of a practical 4-phase VRM