Reduction of Quantization Effects in Digitally Controlled dc-dc Converters using Inductor Current Estimation

Digital control for low-cost high-frequency dc-dc converters requires a reduced number of bit for analog to digital converters (ADCs). By assuming that the sampled variable exhibits a linear behavior during switch-on and switch-off phases, this paper investigates a simple method to increase the ADC resolution using a low resolution digital to analog converter (DAC) and a comparator. The digital estimation is performed using geometrical considerations and assuming the knowledge of the slope of the triangular ripple waveform. The estimation algorithm requires only a rough knowledge of system parameters and it can be easily self-adjusted. Applications to current loop control, VRM control, output voltage control with electrolytic output capacitors are reported. Simulation and experimental results of a synchronous buck converter (1.3 V-10 A) using a field programmable gate array (FPGA) confirm the properties of the proposed investigation