Very high voltage planar devices using field plate and semi-resistive layers: design and fabrication

An efficient junction termination technique for 4 kV devices is presented. The complementarity of a field plate and a semi-resistive layer is shown allowing us to fabricate planar devices with a very high breakdown voltage and to decrease the silicon area consumed. The dynamic behaviour of SIPOS terminated diodes is physically explained and modelled. A solution to improve the dynamic behaviour up to 3000 V/μs is proposed. The following describes the complete design, electrical characteristics and fabrication of 4 kV planar diodes