High-level test generation from VHDL behavioral descriptions

In this paper a method for high-level test generation for systems described in VHDL is presented. First, two test generation algorithms for VHDL processes are presented. The first algorithm works on processes which represent combinational logic whereas the second works on processes which represent sequential logic. The goal of both algorithms is to test all portions of the process body by traversing all the feasible paths. Employing these two algorithms, two new algorithms for system-level test generation for both combinational and sequential systems are presented. The approach employs software metrics as well as signal coverage for interconnections and state and transition coverage for FSMs