Title :
A 6-bit 2GS/s CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques
Author :
Reyes, BenjamiÌn T. ; Tealdi, Lucas ; Paulina, German ; Labat, Emanuel ; Sanchez, Ricardo ; Mandolesi, P.S. ; Hueda, Mario R.
Author_Institution :
Lab. de Comun. Digitales, Univ. Nac. de Cordoba, Cordoba, Argentina
Abstract :
A 6-bit 2-GS/s time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 μm CMOS process. The architecture uses 8 time-interleaved track-and-hold amplifiers (THA), and 16 SAR ADC´s. The chip includes (i) a programmable delay cell array to adjust the interleaved sampling phase, and (ii) a 12 Gbps low voltage differential signaling (LVDS) interface. These blocks make the fabricated ADC an excellent platform to evaluate mixed-signal calibration techniques, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show 33.9 dB of peak signal-to-noise-and-distortion ratio (SNDR) and 192 mW of power consumption at 1.2 V.
Keywords :
CMOS integrated circuits; amplifiers; analogue-digital conversion; calibration; integrated circuit design; integrated circuit measurement; mixed analogue-digital integrated circuits; sample and hold circuits; CMOS time-interleaved ADC; LVDS interface; SAR; THA; TI; analog-to-digital converter; bit rate 12 Gbit/s; high-speed optical system; interleaved sampling phase; low voltage differential signaling interface; mixed-signal calibration technique; noise figure 33.9 dB; power 192 mW; programmable delay cell array; size 0.13 mum; successive approximation register; time-interleaved track-and-hold amplifier; voltage 1.2 V; word length 6 bit; Arrays; CMOS integrated circuits; Calibration; Clocks; Delays; Gain;
Conference_Titel :
Circuits and Systems (LASCAS), 2014 IEEE 5th Latin American Symposium on
Conference_Location :
Santiago
Print_ISBN :
978-1-4799-2506-3
DOI :
10.1109/LASCAS.2014.6820267
