Hardware/software partitioning for performance enhancement

The main objective of hardware/software codesign is to produce systems containing an optimum balance of hardware and software components which work together to achieve a specified behaviour and fulfil specified design criteria-including meeting critical performance targets. This work is concerned with the realisation of a particular class of hardware/software system where the aim is to enhance the performance of critical regions of a software application-this is commonly known as software acceleration. In our case, a critical region of software is part of an application where either a software solution cannot meet the required performance constraints and a hardware solution must be found, or the overall performance can be accelerated by implementing the critical region in hardware. In our approach to hardware/software codesign an application is firstly implemented as a C program and critical regions are identified. The original program can be subsequently partitioned into hardware and software subsystems-where a selected critical region is now implemented in hardware using an FPGA for enhanced performance. We have also implemented an integrated development system to support our codesign methodology, based on a microprocessor and a companion FPGA