Hybrid optical-electrical overlay test structure [for CMOS]

The purpose of this work is to explore the use of electrical test structures for calibrating optical overlay instruments with respect to certain application-dependent errors which are otherwise expected to become a serious impediment to realization of the goals of the National Technology Roadmap for Semiconductors over the next decade. A new hybrid test structure, from which overlay measurements can be extracted electrically, as well as by optical instruments used for inspecting production wafers, has been designed and fabricated with built-in overlay values ranging from -60 to +60 nm. Structures patterned in a single conducting film and having critical-dimension (CD) design-rules ranging from 1.0 to 2.0 pm have been tested. Electrical overlay parameters, derived from multiple step-and-repeat exposure-site measurements, generally match the corresponding optical parameters to within several nanometers, subject to nominal quality of the pattern-replication process. This paper focuses on the analysis of electrical measurements, their dependence on CD design rules, and their comparison with the corresponding measurements made both by a commercial optical-overlay instrument and by a coordinate-measurement system having measurements traceable to absolute dimensional standards