DocumentCode :
2711600
Title :
Transistor aging and reliability in 14nm tri-gate technology
Author :
Novak, S. ; Parker, C. ; Becher, D. ; Liu, M. ; Agostinelli, M. ; Chahal, M. ; Packan, P. ; Nayak, P. ; Ramey, S. ; Natarajan, S.
Author_Institution :
Logic Technol. Dev. Quality & Reliability, Intel Corp., Hillsboro, OR, USA
fYear :
2015
fDate :
19-23 April 2015
Abstract :
This paper details the transistor aging and gate oxide reliability of Intel´s 14nm process technology. This technology introduces Intel´s 2nd generation tri-gate transistor and the 4th generation of high-κ dielectrics and metal-gate electrodes. The reliability metrics reported here highlight reliability gains attained through transistor optimizations as well as intrinsic challenges from device scaling.
Keywords :
MOSFET; ageing; reliability; gate oxide reliability; high-κ dielectrics; metal-gate electrodes; size 14 nm; transistor aging; transistor optimizations; trigate technology; trigate transistor; Degradation; Hot carriers; Integrated circuit reliability; Logic gates; Stress; Transistors; 14nm; Bias Temperature Instability; Fin-FET; High-k; Hot Carriers; Oxide Breakdown; metal gate;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium (IRPS), 2015 IEEE International
Conference_Location :
Monterey, CA
Type :
conf
DOI :
10.1109/IRPS.2015.7112692
Filename :
7112692
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2711600
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