Title :
Matching properties of MOS transistors and delay line chains with self-aligned source/drain contacts
Author :
Bolt, M. ; Cantatore, E. ; Socha, M. ; Aussems, C. ; Solo, J.
Author_Institution :
Faselec AG, Philips Semiconductors, Zurich, Switzerland
Abstract :
This work has shown for the first time that the matched parameter spreads for MOSFETs with and without self-aligned source/drain contacts are identical. From these observations it can be concluded that source/drain series resistance variations do not contribute significantly to MOS transistor mismatch. An example has been given which shows how to apply matching data to circuits. A similar circuit mismatch methodology could be used to analyse yield problems in clock systems of fast digital logic
Keywords :
CMOS integrated circuits; circuit optimisation; delays; impedance matching; integrated circuit design; integrated circuit measurement; integrated circuit testing; integrated circuit yield; CMOS process; MOS transistors; circuit mismatch methodology; circuit optimisation; clock systems; delay line chains; fast digital logic; matched parameter spreads; matching properties; self-aligned source/drain contacts; source/drain series resistance variations; yield problems; CMOS logic circuits; CMOS process; Circuit testing; Delay lines; Electrical resistance measurement; Integrated circuit measurements; Intrusion detection; MOS devices; MOSFETs; Threshold voltage;
Conference_Titel :
Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on
Conference_Location :
Trento
Print_ISBN :
0-7803-2783-7
DOI :
10.1109/ICMTS.1996.535616
