Title :
Circuit design in nanoscale FDSOI technologies
Author :
NikolicÌ, B. ; BlagojevicÌ, M. ; Thomas, O. ; Flatresse, Philippe ; Vladimirescu, Andrei
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, Berkeley, CA, USA
Abstract :
Planar fully-depleted SOI technology with ultra-thin body and buried oxide presents a platform for an energy-efficient design in deeply scaled technologies without major changes in the bulk-CMOS design infrastructure. Good control of short-channel effects with thin transistor body offers a possibility to reduce the supply voltage. Thin buried oxide provides threshold tuning via body bias. Overall design optimality is achieved through sensitivity-based optimization by selecting optimal supplies and thresholds.
Keywords :
CMOS integrated circuits; circuit tuning; integrated circuit design; nanoelectronics; silicon-on-insulator; bulk-CMOS design infrastructure; buried oxide; circuit design; design optimality; nanoscale FDSOI technology; planar fully-depleted SOI technology; sensitivity-based optimization; short-channel effects; supply voltage reduction; thin transistor body; threshold tuning; ultra-thin body; CMOS integrated circuits; Computer architecture; Logic gates; MOSFET; Optimization; Random access memory;
Conference_Titel :
Microelectronics Proceedings - MIEL 2014, 2014 29th International Conference on
Conference_Location :
Belgrade
Print_ISBN :
978-1-4799-5295-3
DOI :
10.1109/MIEL.2014.6842076
