DocumentCode :
2712112
Title :
Methodology to achieve planar technology-like ESD performance in FINFET process
Author :
Jian-Hsing Lee ; Prabhu, Manjunatha ; Korablev, Konstantin ; Singh, Jagar ; Natarajan, Mahadeva Iyer ; Pandey, Shesh Mani
Author_Institution :
GLOBALFOUNDRIES Inc., Malta, NY, USA
fYear :
2015
fDate :
19-23 April 2015
Abstract :
Method for making Finfet ESD performance comparable to bulk planar ESD devices is demonstrated using a simple but effective process. Low FIN silicon volume compared to their counterparts in bulk planar process is compensated with the additional deep implants. The selected ESD devices in Finfet process show competitive ESD performance without any significant cost adder.
Keywords :
MOSFET; electrostatic discharge; silicon; FIN silicon volume; FINFET process; bulk planar ESD device; bulk planar process; deep implant; electrostatic discharge; planar technology-like ESD performance; Electrostatic discharges; FinFETs; Implants; Junctions; Logic gates; Performance evaluation; Silicon; Electrostatic Discharge (ESD); Finfet;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium (IRPS), 2015 IEEE International
Conference_Location :
Monterey, CA
Type :
conf
DOI :
10.1109/IRPS.2015.7112721
Filename :
7112721
Link To Document :
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