Single-phase phase locked loop with dc offset and noise rejection for photovoltaic inverters

Proper work of grid-connected converters requires an accurate detection of phase angle, frequency and amplitude of grid voltage. Phase locked loops (PLLs) based on synchronous reference frame theory can be used for estimation of these grid parameters. One of the issues that could appear during estimation of grid parameters is appearance of DC offset in measured grid voltage. This DC component (offset) is usually entered in PLL structure via measurement and A/D conversion process. Undesirable induced DC offset could appear as part of the reference sine current of photovoltaic inverters or other grid-connected converters. A lot of standards define allowed PV inverter´s DC current injection in the grid. In this study, we propose an improved PLL structure with capability to fully reject DC offset and noise which could appear in measured input grid voltage. The key component of the proposed PLL is two-phase generator with a closed control loop for DC offset and noise rejection. Obtained simulation and experimental results show that the proposed PLL structure can solve important issues of presence of noise and DC offset in measured grid voltage. The proposed PLL structure shows excellent dynamical performances in conditions of fast changes of grid parameters.