Title :
Product-level reliability estimator with budget-based reliability management in 20nm technology
Author :
Jae-Gyung Ahn ; Ming Feng Lu ; Navale, Nitin ; Graves, Dawn ; Ping-Chin Yeh ; Chang, Jonathan ; Pai, S.Y.
Author_Institution :
FPGA Dev. & Silicon Technol. Group, Xilinx, Inc., San Jose, CA, USA
Abstract :
Product-level Reliability Estimator (PLRE) has been built for 20nm technology product. With PLRE, users can estimate failure rate of the chip with various use conditions. EDA tools are used to estimate each block´s reliability budget, in terms of effective area for TDDB and effective number for EM which are to be used in building PLRE. Budget-based reliability check procedure was explained, which let designers have more room for reliability to get better circuit performance. Results of PLRE show that EM and MOL TDDB can be an actual risk in specific use condition.
Keywords :
MOSFET; electric breakdown; electromigration; failure analysis; semiconductor device reliability; EDA tools; EM; MOL TDDB; MOSFET; PLRE; block reliability budget; budget-based reliability check procedure; budget-based reliability management; electromigration; failure rate estimation; product-level reliability estimator; size 20 nm; time-dependent-dielectric breakdown; Failure analysis; Integrated circuit reliability; Mathematical model; Reliability engineering; Stress; Wires; Electromigration; HTOL; MOL TDDB; TDDB; failure rate; product reliability; reliability budget;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2015 IEEE International
Conference_Location :
Monterey, CA
DOI :
10.1109/IRPS.2015.7112762
