NBTI and HCD aware behavioral models for reliability analysis of analog CMOS circuits

For safety-critical applications with long operational lifetimes the analysis of aging aspects caused by NBTI and HCD is moving into the focus of the designer. The increasing complexity of modern analog and mixed-signal circuits makes a reliability analysis on transistor level for complex systems quite challenging. In this paper we present a method using Box-Behnken Designs and Response Surface Modeling with exponential function interpolation. This approach enables accelerated reliability analysis on system level. A tool is introduced to support the behavioral model generation process. The derived model includes information on degradation and process variations. The method is demonstrated for a current-mirror and a CS amplifier to quantify the degradation influence. The accuracy of the behavioral models and the age-dependent yield of the circuits is determined.