DocumentCode
2713558
Title
Backside thinning of GaAs wafer by lapping using DOE approach
Author
Prakash, Siddi Jai ; Tyagi, Rinki ; Gupta, Ashish
Author_Institution
Dept. of Electron. & Commun. Eng., Netaji Subhas Inst. of Technol., Delhi, India
fYear
2011
fDate
28-30 Jan. 2011
Firstpage
1
Lastpage
4
Abstract
In this paper, a procedure to achieve efficient and high quality backside thinning of GaAs wafer using the lapping machine is demonstrated and the precautions and set of rules to be followed to utilize it productively are given. We selected the 4 main parameters affecting the lapping process i.e. concentration of the slurry (5 μm Al2O3 used here), pressure on the lapping plate, drop rate from the cylinder, rotations per minute of the lapping plate as the major independent variables and statistically designed the experiment in order to get the best lapping rate. The lapping process was carried out using Logitech PM2A lapping and polishing machine. Best lapping rate of 2 μm/min was observed in the case when rpm was kept low and all other parameters high. Thus this work provides a set of key notes and observations necessary for the lapping of GaAs wafer using the Logitech PM2A machine with the help of the statistical data of the Design of Experiment (DOE) results to achieve the best lapping rate.
Keywords
III-V semiconductors; aluminium compounds; design of experiments; etching; gallium arsenide; lapping (machining); polishing machines; semiconductor device manufacture; Al2O3; DOE; GaAs; GaAs wafer; Logitech PM2A lapping; Logitech PM2A machine; backside thinning; design of experiment; lapping machine; lapping plate; polishing machine; Aluminum oxide; Gallium arsenide; Heat sinks; Lapping; Slurries; Surface treatment; US Department of Energy; DOE; FET; Lapping; Power Dissipation;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics (IICPE), 2010 India International Conference on
Conference_Location
New Delhi
Print_ISBN
978-1-4244-7883-5
Type
conf
DOI
10.1109/IICPE.2011.5728072
Filename
5728072
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