Title :
Logic model optimization for LSSD structures
Author :
Huang, Su-Hsuan ; Forlenza, Donato ; Waicukauski, John ; Pete, Cathleen
Author_Institution :
IBM Corp., East Fishkill, NY, USA
Abstract :
A method that optimizes the logical description of an LSSD (level-sensitive scan design) structure is described. The logic model thus created results in improved efficiency of test generation, fault simulation, and failure diagnosis. Extensive testing with this system has resulted in logic-gate-count reduction up to 40%, reduction in simulation CPU time by a factor of 2, and improvement in efficiency and effectiveness in the testing environment. Significant model gate count is achieved with only a minor increase in the CPU time
Keywords :
fault location; logic design; logic gates; logic testing; LSSD structures; efficiency; failure diagnosis; fault simulation; level-sensitive scan design; logic model; logic-gate-count reduction; logical description; simulation CPU time; test generation; Circuit simulation; Circuit testing; Clocks; Design optimization; Latches; Logic circuits; Logic gates; Logic testing; Software algorithms; Test pattern generators;
Conference_Titel :
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/VTSA.1989.68601
