DocumentCode :
2714686
Title :
A universal abstract-time platform for real-time neural networks
Author :
Rast, A.D. ; Khan, M.M. ; Jin, X. ; Plana, L.A. ; Furber, S.B.
Author_Institution :
Sch. of Comput. Sci., Univ. of Manchester, Manchester, UK
fYear :
2009
fDate :
14-19 June 2009
Firstpage :
2611
Lastpage :
2618
Abstract :
High-speed asynchronous hardware makes it possible to virtualise neural networks´ temporal dynamics as well as their structure. Through SpiNNaker, a dedicated neural chip multiprocessor, we introduce a real-time modelling architecture that makes the neural model run on the device independent of the hardware specifics. The central features of this modelling architecture are: native concurrency, ability to support very large (Gt 109 neurons) networks, and decoupling of the temporal and spatial characteristics of the model from those of the hardware. It circumvents a virtually fatal tradeoff in large-scale neural hardware between model support limitations or scalability limitations, without imposing a synchronous timing model. The chip itself combines an array of general-purpose processors with a configurable asynchronous interconnect and memory fabric to achieve true on- and off-chip parallelism, universal network architecture support, and programmable temporal dynamics. An HDL-like concurrent configuration software model using libraries of templates, allows the user to embed the neural model onto the hardware, mapping the virtual network structure and time dynamics into physical on-chip components and delay specifications. Initial modelling experiments demonstrate the ability of the processor to support real-time neural processing using 2 different neural models. The complete system is therefore an environment able, within a wide range of model characteristics, to model real-time dynamic neural network behaviour on dedicated hardware.
Keywords :
multiprocessing systems; neural chips; SpiNNaker; configurable asynchronous interconnect; dedicated hardware; dedicated neural chip multiprocessor; general-purpose processors; large-scale neural hardware; memory fabric; neural network temporal dynamics; programmable temporal dynamics; real-time neural networks; real-time neural processing; synchronous timing model; universal abstract-time platform; universal network architecture; very large networks; virtual network structure; Computer architecture; Concurrent computing; Fabrics; Large-scale systems; Neural network hardware; Neural networks; Neurons; Page description languages; Scalability; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks, 2009. IJCNN 2009. International Joint Conference on
Conference_Location :
Atlanta, GA
ISSN :
1098-7576
Print_ISBN :
978-1-4244-3548-7
Electronic_ISBN :
1098-7576
Type :
conf
DOI :
10.1109/IJCNN.2009.5179067
Filename :
5179067
Link To Document :
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