Title :
Testing VLSI chips with weighted random patterns
Author :
Waicukauski, John A. ; Motika, Franco
Author_Institution :
IBM Corp., East Fishkill, NY, USA
Abstract :
A test methodology utilizing weighted random patterns (WRP) has recently been developed for level-sensitive scan design (LSSD) logic devices. An automated WRP test generation system combined with a tester modified to apply weighted random patterns has been implemented for the production testing of high-performance VLSI (very-large-scale-integration) chips. The advantages observed in using WRP are the following: (1) It provides full stuck fault coverage, unlike a random pattern test, and improves the coverage of nonmodeled faults compared to a deterministic test; (2) it can apply at least an order of magnitude more patterns to a device than a DET tet in less times on present testers, with many times fewer test data; (3) the computer time spent to generate the WRP test data is small compared to a deterministic test; (4) these advantages are realized with no chip circuit overhead other than that required for LSSD. WRP testing has resulted in a higher quality test at a significantly lower cost
Keywords :
VLSI; integrated circuit testing; integrated logic circuits; logic testing; production testing; VLSI chips; chip circuit overhead; deterministic test; high-performance VLSI; level-sensitive scan design; production testing; stuck fault coverage; test methodology; weighted random patterns; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Logic devices; Logic testing; Production systems; System testing; Test pattern generators; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/VTSA.1989.68602
