Title :
Test generation for presettable synchronous sequential circuits
Author :
Wang, Jhing-Fa ; Kuo, Tah-Yuan ; Chen, Pao-Chuan ; Lee, Jau-Yien
Author_Institution :
Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
A test generation system for presettable synchronous sequential circuits is presented. The main goals is to obtain a test sequence as short as possible for a given circuit. To do this, the authors introduce a measure called minimum output distance (MOD), which can help select the target faults to test so that the expected test length and computing time can be reduced. Experimental results for several circuits are given, showing that the system can achieve very high fault coverage within a reasonable time
Keywords :
fault location; logic testing; sequential circuits; computing time; fault coverage; minimum output distance; presettable synchronous sequential circuits; target faults; test generation system; test length; test sequence; Circuit faults; Circuit testing; Combinational circuits; Computational modeling; Costs; Design for testability; Sequential analysis; Sequential circuits; Synchronous generators; System testing;
Conference_Titel :
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/VTSA.1989.68603
