Power supply analysis of a large area integrated circuit

This paper introduces the power supply analysis of a large area integrated circuit (LAIC) used in a rapid prototyping platform for electronic systems. User integrated circuits deposited on this active LAIC surface receive power through configurable IOs. Strategies to distribute power all over a LAIC of the size of an entire wafer are described, modeled and their performances evaluated. Different scenarios have been investigated considering technological and physical constraints. A strategy has been implemented in a mature and low-cost 7-metal layers CMOS 0.18 μm technology. It uses advanced Through Silicon Vias (TSVs) to support up to 1000 W of power consumption. Detailed power analysis is provided. It is based on a finite element model (FEM) of the power grid. The FEM simulations allow determining the power density flowing through TSVs, as well as that flowing in the metal stripes which allow sizing these components in a way that meets electromigration and IR drop design constraints.