Design and implementation of redundant multiprocessor interconnects in a high capacity router

This paper is about multiprocessor interconnects for the high capacity router built on ATCA (advanced telecom computing architecture) platform. Multiprocessor interconnection in ATCA brings some design issues when it comes to satisfying the constraint and specification of the ATCA platform. In the multiprocessor communication, most transfers are from one port to the other ports or the opposite direction (usually between a main processor and local processors on line cards). Congestion may happen when interprocessor communication packets from local processors are simultaneously heading for a main processor. In order to manage or alleviate the congestion, bandwidth for interprocessor communication should be increased and QoS mechanisms should be introduced in multiprocessor interconnects. This study suggests several methods to build multiprocessor interconnects in ATCA and discusses them in the view of redundancy, congestion handling ability, and implementation feasibility