DocumentCode :
2715732
Title :
A phase-based single-bit Delta-Sigma ADC architecture
Author :
Lin, Yiqiao ; Liao, De-Wen ; Hung, Chung-Chih ; Ismail, Mohammed
Author_Institution :
Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH, USA
fYear :
2011
fDate :
26-29 June 2011
Firstpage :
406
Lastpage :
409
Abstract :
A Phase-based Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) adopting a Delay-Locked-Loop (DLL) mechanism is presented. It is realized by a modification of a DLL using a Voltage-Controlled Delay Line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed ΔΣ ADC achieved 7.99 bits resolution with OSR =32 for a 10 MHz signal bandwidth.
Keywords :
circuit noise; delay lock loops; delays; delta-sigma modulation; jitter; DLL; analog-digital converter; charge pump; delay-locked-loop mechanism; feedback path; phase-based single-bit delta-sigma architecture; quantization noise shaping; reference jitter shaping; voltage-controlled delay line; Charge pumps; Clocks; Jitter; Noise; Quantization; Transfer functions; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International
Conference_Location :
Bordeaux
Print_ISBN :
978-1-61284-135-9
Type :
conf
DOI :
10.1109/NEWCAS.2011.5981256
Filename :
5981256
Link To Document :
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