Improved circuitry for soft error correction in combinational logic in pipelined designs

This paper proposes the improvement of the method for soft error correction in the combinational circuit part of sequential circuits as described in [1], for which fault-tolerant master-slave elements are used. The errors in the combinational circuit part are detected by an error detection circuit and the error signal blocks the clock signal as long as the error exists. The system remains in its previous correct state and no complex recovery of the system is needed. In this paper we show how the method can be modified in such a way that it can be integrated into the standard industrial design flow and we demonstrate how the method can be favourably applied to a pipeline with different stages. Experimentally it is shown that the number of corrected errors can be increased by a factor of 4.22.