Three-dimensional image processing VLSI system with reconfigurable memory architecture and RAM/ROM synthesis design

In this paper, we propose new RAM/ROM synthesis system with reconfigurable memory architecture for three-dimensional (3D) image processing VLSI system. To enable flexible image data operation, suitable input/output data control is critical for high performance image processing system. Fast speed 3D VLSI system also requires effective pipeline data control. Thus new RAM/ROM codesign synthesis architecture is realized by specific arrangement with RAM, ROM, pin and interconnection. Flip-Flop control, clock buffer insertion and critical signal route have been improved to enhance whole system speed. The reconfigurable memory system is also proposed to enable fast operation speed and raise chip system robustness. 3D image processing VLSI system can also be improved by suitable data storage and pipeline control flow in reconfigurable RAM/ROM synthesis system. Chip simulation experiments show efficient results with 247.728 mW power consumption and 50 MHz operation frequency. Practical chip test confirms that new RAM/ROM system can successfully realize chip inner fetch function and data flow control to improve 3D reconfigurable system efficiency. Better system flexibility can also realized by specific reconfigurable control operation and precise 3D stacking layer design.