• DocumentCode
    2716310
  • Title

    Power-time tradeoffs in digital filter design and implementation

  • Author

    Anderson, M.S. ; Summerfield, S.

  • Author_Institution
    Dept. of Eng., Warwick Univ., Coventry, UK
  • fYear
    1995
  • fDate
    34852
  • Firstpage
    42583
  • Lastpage
    42587
  • Abstract
    In this paper, a comparison is made between the average power dissipation of FIR, IIR and lattice wave digital filters meeting the same specifications. The power dissipation of various architectures is estimated and tradeoffs between the sample rate and power are performed by varying the degree of pipelining and concurrency. Estimation of the power dissipation is done at a high-level, avoiding common problems
  • Keywords
    CMOS digital integrated circuits; FIR filters; IIR filters; digital filters; lattice filters; pipeline processing; FIR filters; IIR filters; average power dissipation; concurrency; digital filters; filter design; lattice wave filters; pipelining; power-time tradeoffs; sample rate;
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Low Power Analogue and Digital VLSI: ASICS, Techniques and Applications, IEE Colloquium on
  • Conference_Location
    London
  • Type

    conf

  • DOI
    10.1049/ic:19950795
  • Filename
    478155
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2716310