Title :
Use of test structures for a wafer-level-reliability monitoring
Author :
Papp, A. ; Bieringer, F. ; Koch, D. ; Kammer, H. ; Pohle, H. ; Schlemm, A. ; Schneegans, M. ; Vogt, H.
Author_Institution :
Semicond. Group, Siemens AG, Munich, Germany
Abstract :
To fulfil future quality requirements, the waferfabs need a fast feedback of reliability data additionally to that already established for yield data. Wafer-level-reliability programs for test structures with highly accelerated stress are necessary to reach very short test periods. A concept with a variable drop-in test chip is described. By means of two examples, gate oxide integrity and electromigration, challenges and solutions are presented. The charge to breakdown distribution offers a way to characterize early failures rapidly. The EM test on wafer level allows life time predictions to remain useful
Keywords :
electric breakdown; electromigration; failure analysis; integrated circuit reliability; integrated circuit testing; life testing; production testing; quality control; accelerated stress; charge to breakdown distribution; early failures; electromigration; gate oxide integrity; life time predictions; quality requirements; test periods; test structures; variable drop-in test chip; wafer-level-reliability monitoring; Automatic testing; Circuit testing; Electromigration; Feedback; Life estimation; Life testing; Monitoring; Production; Semiconductor device reliability; Stress;
Conference_Titel :
Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on
Conference_Location :
Trento
Print_ISBN :
0-7803-2783-7
DOI :
10.1109/ICMTS.1996.535658
