A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 $\mu{\rm m}$ CMOS

This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm² QRD chip, fabricated in 0.13 μm 1P8M CMOS technology, demonstrate that the proposed design for 4×4 complex matrices attains the lowest reported processing latency of 40 clock cycles (144 ns) at 278 MHz and dissipates 48.2 mW at 1.3 V supply and 25°C. It outperforms all of the previously published QRD designs by offering the highest QR processing efficiency.