Single Electron Transistor analytical model for hybrid circuit design

Author

Bounouar, M.A. ; Calmon, F. ; Beaumont, A. ; Guilmain, M. ; Xuan, W. ; Ecoffey, S. ; Drouin, D.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Sherbrooke, Sherbrooke, QC, Canada

fYear

2011

fDate

26-29 June 2011

Firstpage

506

Lastpage

509

Abstract

A novel analytical and compact model of Single Electron Transistor (SET) is developed and implemented in Verilog-A language for use in hybrid SET-CMOS logic circuit design. The model is based on the steady state Master-Equation (ME). The implementation of this original and simple model, taking into account physical characteristics of tunnel junctions and the thermionic emission, has faithfully reproduced the behavior of metallic SET operating at room temperature. The hybrid SET-CMOS universal logic gate cell is analyzed to illustrate the efficiency of this compact SET model.

Keywords

CMOS logic circuits; hardware description languages; semiconductor device models; single electron transistors; thermionic emission; ME; SET-CMOS logic circuit design; Verilog-A language; hybrid circuit design; single electron transistor analytical model; steady state master-equation; temperature 293 K to 298 K; thermionic emission; tunnel junctions; Analytical models; CMOS integrated circuits; Integrated circuit modeling; Junctions; Logic gates; Semiconductor device modeling; Tunneling; Coulomb Blockade; Hybrid SET-CMOS circuit design; SET modeling; Single Electron Transistor (SET);

fLanguage

English

Publisher

ieee

Conference_Titel

New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International

Conference_Location

Bordeaux

Print_ISBN

978-1-61284-135-9

Type

conf

DOI

10.1109/NEWCAS.2011.5981330

Filename

5981330