VLSI implementation of a reversible variable length encoder/decoder

Variable length codes (VLCs) are known for their efficient compression, but are susceptible to noisy environments due to synchronization losses that can occur from bit error propagation. The interest in reversible variable length codes (RVLCs) has come about due to the growing need for wireless exchange of compressed image and video signals over noisy channels and the ability for RVLCs to provide greater error robustness than their non-reversible counterparts (VLCs). With the current ITU H.263+ and ISO MPEG-4 standards already using RVLCs, low power implementations of the RVLC are essential in providing error robustness in real-time systems, while minimizing power consumption. This paper presents the first published VLSI architectures of a low power reversible variable length encoder and decoder. Results show power consumption of less than 1 mW for both encoder and decoder, with an additional 65% increase in area for the decoder over that of a conventional VLD design