Optimum test structure design for CMOS parasitic transistor characterisation

As CMOS active transistor channel lengths continue to shrink with each technology generation, there is typically a reduction in key layout pitches, to increase packing density and thereby reduce costs. Maintaining adequate lateral device isolation is central to this scaling strategy. One of the problems associated with scaling the active area (AA) pitch is the increased likelihood of parasitic field transistor leakage, either due to low field threshold voltages or field punch through. The key rule is the AA space, as this is one of the major factors in determining the lateral isolation. For 0.5 μm geometries, a typical AA space is 0.9 μm, reducing to 0.7 or 0.6 μm for 0.35 μm design rules. It is thus essential to be able to fully characterise and understand parasitic leakage currents in such structures to ensure they are kept to a minimum. This paper seeks to define an optimum set of test structures that can be used to measure the different parasitic leakage components. The authors outline the formation of the parasitic field device and the main leakage mechanisms. They show how the level of leakage depends on the structure, particularly for gated devices. The optimum structure, which gives worst case leakage, is defined. The authors describe how the different currents measured during test can be used to determine the type of leakage, and hence lend themselves to an automated test