Test structures for automated contactless inline wafer inspection

Simple but unique and space-saving microelectronic test structures were designed to afford automated inline contactless wafer inspection in a Scanning Electron Microscope (SEM) for rapid electrical defect-monitoring in the voltage contrast (VC) mode, along with in situ defect-isolation and -characterization capabilities. Such an automated technique can support accelerated yield learning on sub-0.25 μm-rule designs as the defects get below the optical resolutions. The system is also capable of the traditional visual inspection in the secondary-electron emission mode, affording the determination of the transfer coefficients between optical inspection and electrical faults