Title :
Low-voltage ADC for sample to serial interface applications
Author_Institution :
Dept. of Electr. Eng., Assiut Univ., Egypt
Abstract :
This paper presents a CMOS implementation of a cyclic analog-to-digital converter (ADC). The sampled-hold (S/H) circuit is based on a switched-MOSFET (SM) technique, which is appropriate for low-voltage operation. The proposed analog-to-digital converter architecture works as a sample (analog) to serial (digital) interface. The proposed ADC circuit is designed and simulated by using double-polysilicon double-metal 0.8 μm CMOS technology with 500 kbit/sec. The estimated power consumption is 20 μW from ±0.75 V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit CAD; circuit simulation; integrated circuit design; integrated circuit modelling; low-power electronics; sample and hold circuits; -0.75 to 0.75 V; 0.8 micron; 20 muW; 500 kbit/s; CMOS low-voltage ADC architecture; S/H circuits; algorithmic A/D converter power consumption; cyclic analog-to-digital converters; double-polysilicon double-metal CMOS technology; sample to serial interface applications; sample-hold circuits; sampled-hold circuits; Analog-digital conversion; CMOS technology; Circuit simulation; Clocks; Energy consumption; Samarium; Signal processing algorithms; Switches; Switching circuits; Voltage;
Conference_Titel :
Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on
Print_ISBN :
0-7695-1807-9
DOI :
10.1109/SBCCI.2002.1137668
