A parallel processing architecture for FSS block-matching motion estimation

Author

Dhahri, Salah ; Zitouni, Abdelkrim ; Tourki, Rached

Author_Institution

Electron. & M icro- Electron. Lab., Fac. of Sci. of Monastir, Monastir, Tunisia

fYear

2011

fDate

22-25 March 2011

Firstpage

1

Lastpage

5

Abstract

Motion Estimation (ME) is a key factor for achieving enhanced compression ratio. However, ME involves high computational complexity. The main goal is to reduce the execution time without reducing image quality. In this paper, a proposed high parallel processing architecture is presented for four-step search block-matching motion estimation. The proposed method develops an architecture which using 9 processing-elements (PE) and processes them in parallel. The architecture has been simulated and synthesized with VHDL and ASIC (CMOS 45nm). Synthesize results show that the proposed architecture achieves a high performance for real time motion estimation.

Keywords

application specific integrated circuits; computational complexity; data compression; hardware description languages; image coding; image enhancement; image matching; motion estimation; parallel processing; ASIC; CMOS; FSS block-matching motion estimation; VHDL; compression ratio; computational complexity; image quality reduction; parallel processing architecture; size 45 nm; Algorithm design and analysis; Clocks; Computer architecture; Delay; Frequency selective surfaces; Logic gates; Motion estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Systems, Signals and Devices (SSD), 2011 8th International Multi-Conference on

Conference_Location

Sousse

Print_ISBN

978-1-4577-0413-0

Type

conf

DOI

10.1109/SSD.2011.5981484

Filename

5981484