An Efficient Hardware Design for Euclidean Key Equation Solver in Reed-Solomon Decoders

Reed-Solomon codes have been widely used in many communication applications such as satellite communications, fixed broadband wireless access, etc. After obtaining the syndrome polynomial, there are approaches to solve the key equation for error locations and error magnitude. Two most well known approaches are the Euclidean and Berlekamp-Massey (BM) algorithms. This paper presents an efficient hardware implementation for the Euclid´s algorithm. According to the design results, the proposed low latency design has only about 72.5% clock cycles of those in H. Lee (2003) and Hsie-Chia Chang and Chen-Yi Lee (2001). In addition, the chip synthesis report shows the proposed design has only 63.6% gate count of H. Lee (2003) and 27% gates of Hsie-Chia Chang and Chen-Yi Lee (2001), respectively. The new design is also compared to the BM algorithm and exhibits shorter latency in several erasure cases