Title :
A bipartite, differential IDDQ testable static RAM design
Author :
Al-Assadi, W.K. ; Jayasumana, A.P. ; Malaiya, Y.K.
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
Abstract :
IDDQ (Defect Detection by Quiescent power supply current measurement), or current testing, has emerged in the last few years as an effective technique for detecting certain classes of faults in high-density ICs. In this paper, a testable design that enhances the IDDQ testability of static random access memories (SRAMs) for off-line testing as proposed. To achieve high accuracy and a test speed approaching the system operational speed, the memory is partitioned for comparison of IDDQ values. Parallel write/read operations are used to activate possible faults, while quiescent power supply currents from two blocks are compared
Keywords :
SRAM chips; fault diagnosis; fault location; integrated circuit testing; SRAM; accuracy; bipartite differential IDDQ testable static RAM design; current testing; defect detection; fault activation; high-density IC fault detection; memory partitioning; off-line testing; parallel write/read operations; quiescent power supply current measurement; static random access memories; system operational speed; test speed; testability; Circuit faults; Circuit testing; Differential amplifiers; Fault detection; Performance evaluation; Random access memory; Read-write memory; Size measurement; System testing; Voltage;
Conference_Titel :
Memory Technology, Design and Testing, 1995., Records of the 1995 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-7102-5
DOI :
10.1109/MTDT.1995.518079
