A 5 Gb/s 9-port application specific SRAM with built-in self test

Author

Wood, Steven W. ; Gibson, G. F Randall ; Adham, Saman M I ; Nadeau-Dostie, Benoit

Author_Institution

Northern Telecom, Ottawa, Ont., Canada

fYear

1995

fDate

7-8 Aug 1995

Firstpage

68

Lastpage

73

Abstract

Describes the architecture of a time-slot interchange (TSI) SRAM for a SONET switching application and its associated BIST architecture. To reduce the number of data RAMs required for full switching, the memory throughput is boosted by providing multiplexed access to the core at twice the system clock rate. The nature of the memory requires a novel BIST architecture to ensure full test coverage and ensure easy access of the BIST function at different levels of system integration

Keywords

SONET; SRAM chips; application specific integrated circuits; built-in self test; integrated circuit testing; memory architecture; telecommunication computing; telecommunication switching; time division multiplexing; 5 Gbit/s; 9-port SRAM; BIST architecture; SONET switching application; application-specific SRAM; built-in self test; core multiplexed access; data RAMs; memory throughput; system clock rate; system integration levels; test coverage; time-slot interchange SRAM architecture; Automatic testing; BiCMOS integrated circuits; Built-in self-test; CMOS technology; Clocks; Decoding; Power dissipation; Power generation; Random access memory; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1995., Records of the 1995 IEEE International Workshop on

Conference_Location

San Jose, CA

Print_ISBN

0-8186-7102-5

Type

conf

DOI

10.1109/MTDT.1995.518084

Filename

518084