Multi-objective mapping for matrix-based nanocomputer architectures

In this paper, we propose a method for the multi-objective mapping of applications onto matrix-based nanocomputer architectures. These architectures are composed from reconfigurable logic cells interconnected according to a given topology. The power consumption and data propagation delay of each cell depend on its internal function, e.g. NAND, OR, etc. By taking into account these cell characteristics, the mapping method optimizes power consumption, critical path delay and area of the whole system. We experimentally prove that the proposed method is efficient for generating mapping solutions with good trade-off between the optimized metrics. Furthermore, the method allows the comparison of matrix size and interconnect topologies in nanocomputer architectures, and thus aims to facilitate the development of such architectures. Experimental results demonstrate 38% of power reduction for systolic array and 44% of critical path delay improvement for the “Cell Matrix”.