A structural test methodology for SRAM-based FPGAs

Summary form only given. This presentation focuses on SRAM-based FPGAs. Their simplicity and flexibility for user changes in the field make this type of FPGA a very popular choice among designers. The architecture and design of these devices have been widely investigated during the last decade, but their test challenges have received less attention. Only recently researchers have addressed the problem of testing FPGAs after manufacturing, in other words, before user programming of specific functions. Testing before programming presents a wide spectrum of problems, for which a number of researchers have proposed innovative solutions. Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing various configurations (programmings) of the FPGA. But changing configurations incurs reprogramming costs. So the fundamental question for FPGA testing is how can we determine the minimum number of test configurations and corresponding vector test sequences that will cover all the faults of a given FPGA´s fault model? Solutions are presented in the presentation for various architectural elements of SRAM-based FPGAs.