Title :
Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs
Author :
Cockburn, Bruce F.
Author_Institution :
Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
Abstract :
Describes four new test algorithms that detect different classes of physical neighborhood pattern-sensitive faults (PNPSFs) in n×1 random-access memories (RAMs). All four tests assume that the storage cells are arranged in a rectangular grid. The first two tests assume further that the mapping from logical cell addresses to physical cell locations is known, whereas the second two tests allow the row and column addresses for the square grid to be separately scrambled in any arbitrary way unknown to the tester. The first test has length (97 5/9)n and detects all single active PNPSFs. The second test has length 121 5/9 and detects all single active, static and passive PNPSFs. The third test has a length of approximately 8.0n(log2n)2 and detects all single scrambled active PNPSFs. The fourth test has a length of roughly 8.4n(log2n)2.322 and detects all single scrambled active, static and passive PNPSFs
Keywords :
circuit testing; fault diagnosis; random-access storage; column addresses; deterministic tests; fault detection; logical cell address to physical cell location mapping; physical neighborhood pattern-sensitive faults; random-access memories; rectangular grid; row addresses; scrambled active faults; scrambled passive faults; scrambled static faults; single active faults; single passive faults; single static faults; storage cells; test length; Circuit faults; Circuit testing; Electrical fault detection; Failure analysis; Fault detection; Leakage current; Logic testing; Random access memory; Read-write memory; Semiconductor device testing;
Conference_Titel :
Memory Technology, Design and Testing, 1995., Records of the 1995 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-7102-5
DOI :
10.1109/MTDT.1995.518092
