DocumentCode :
2718708
Title :
Re2DA: Reliable and reconfigurable dynamic architecture
Author :
Pham, Hung-Manh ; Devaux, Ludovic ; Pillement, Sébastien
Author_Institution :
IRISA, Univ. of Rennes I, Lannion, France
fYear :
2011
fDate :
20-22 June 2011
Firstpage :
1
Lastpage :
6
Abstract :
Exploiting partial reconfiguration of commercial FPGAs allows the construction of dynamic multi-processor system-on-chip (MPSoC). This solution offers many advantages such as: low development costs and maintains flexibility as well as high computation power. However, FPGAs are susceptible to electronic particles which can toggle configuration bit values and hence change the correct function of the design. Moreover, that could be important in critical applications which require safety and security. Hence using FPGA requires to integrate fault-tolerance schemes into the system. The reliable MPSoC system called Re2DA, presented in this paper, guarantee the system operation by the use of dynamic reconfiguration. Nearly no hardware overhead is required to perform fault-tolerant feature in the system while timing overhead is kept relatively low.
Keywords :
field programmable gate arrays; multiprocessing systems; reconfigurable architectures; system-on-chip; FPGA; MPSoC; Re2DA; electronic particles; fault-tolerance schemes; multiprocessor system-on-chip; reconfigurable dynamic architecture; Computer architecture; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Hardware; Program processors; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011 6th International Workshop on
Conference_Location :
Montpellier
Print_ISBN :
978-1-4577-0640-0
Type :
conf
DOI :
10.1109/ReCoSoC.2011.5981519
Filename :
5981519
Link To Document :
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