Design considerations for high-performance low-power silicon-on-insulator gate arrays

Silicon-on-insulator (SOI) provides capabilities for high-performance low-power ICs due to reduced capacitance. Significant differences between SOI and bulk technologies impact the design of gate arrays. The comparison of several microarchitectures for representative logic cells results in a variation of area or interconnect efficiency by up to 50 percent. Power supply noise introduced by switching currents is a severe problem in SOI, especially where low-power high-performance dynamic logic is employed. To reduce this, we propose a “charge tank” power supply structure, providing buffering capacitance close to the switching device