Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware — Experiences on teaching and research

Digital data hiding algorithms have recently received attention of the research community as an alternative to fight the piracy problem in the Internet era. Several data hiding applications, such as broadcasting monitoring and live performance watermarking, require a real-time multi-channel behavior, also new applications are constantly pushing the limits of available computing systems. This motivates the research on custom architectures, being reconfigurable logic a good option to implement such processing systems. This paper introduces the field of digital data hiding, including a brief review on hardware based architectures and a discussion of the challenges of implementing custom architectures for this type of applications. Also, the authors´ experience in teaching and research on hardware architectures for digital data hiding algorithms at the MSc Program on Computer Science at INAOE is discussed.