Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA

Cryptographic devices are vulnerable to Differential Power Attacks (DPA). To resist these attacks, the Wave Dynamic Differential Logic (WDDL) has been proposed. However, the limitation of this technique is that it requires balanced routing of the dual rail interconnect between gates, to obtain equal propagation delays and power consumption on differential signals. This paper addresses the problem of routing balance in Mesh FPGA. First, we perform a dual placement in cluster based Mesh FPGA. Then, we propose a differential routing method which achieves a perfectly balanced routed signals in terms of wire length and switch number.