RecoNoC: A reconfigurable network-on-chip

Author

Vancayseele, Robbe ; Farisi, Brahim Al ; Heirman, Wim ; Bruneel, Karel ; Stroobandt, Dirk

Author_Institution

ELIS Dept., Ghent Univ., Ghent, Belgium

fYear

2011

fDate

20-22 June 2011

Firstpage

1

Lastpage

2

Abstract

This article presents the design of RecoNoC: a compact, highly flexible FPGA-based network-on-chip (NoC), that can be easily adapted for various experiments. In this work, we enhanced this NoC with dynamically reconfigurable shortcuts. These can be used to alter the NoC´s topology to adapt to the system´s communication needs. The design has been implemented and tested on a Xilinx Virtex-2 Pro FPGA, using the TMAP dynamic datafolding toolflow to automatically generate the reconfigurable hardware and the software reconfiguration procedures. The results show that, using dynamic datafolding, the overhead of introducing this shortcut mechanism is limited.

Keywords

field programmable gate arrays; integrated circuit design; logic testing; network topology; network-on-chip; reconfigurable architectures; NoC topology; RecoNoC design; TMAP dynamic datafolding toolflow; Xilinx Virtex-2 Pro FPGA; reconfigurable network-on-chip; software reconfiguration; Delay; Field programmable gate arrays; Network topology; Routing; System-on-a-chip; Table lookup; Topology; FPGA; Network-on-Chip; Run-time Reconfiguration; TMAP; dynamic data folding;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011 6th International Workshop on

Conference_Location

Montpellier

Print_ISBN

978-1-4577-0640-0

Type

conf

DOI

10.1109/ReCoSoC.2011.5981529

Filename

5981529