Title :
Design methodology of a test chip for a portable 8ns 10 ports register file
Author :
Lucas, L. ; Greiner, A.
Author_Institution :
Lab. MASI/CAO-VLSI, Univ. Pierre et Marie Curie, Paris, France
Abstract :
This paper presents the design methodology used to implement a test chip for a multiport register file, as well as, the motivation of the project. The register file contains 6 read buses, 4 write buses, and 64 words of 32 bits. A built-in-self test scheme has been used to validate the register file. The final test chip contains 65000 transistors. The complete design including high level models took one man-month
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; built-in self test; circuit layout CAD; integrated circuit design; integrated circuit testing; logic CAD; logic testing; reduced instruction set computing; 8 ns; BIST scheme; built-in-self test scheme; design methodology; multiport register file; portable register file; read buses; test chip; write buses; Automatic testing; Built-in self-test; Circuit testing; Computer aided instruction; Design methodology; Latches; Read-write memory; Registers; Timing; VLIW;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518131
