Notice of Violation of IEEE Publication PrinciplesThe co-simulation interface SystemC/Matlab applied in JPEG algorithm

Notice of Violation of IEEE Publication Principles

"The Co-Simulation Interface SystemC/Matlab Applied In JPEG Algorithm"
by Walid Hassairi, Moncef Bousselmi, Mohamed Abid
in the Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) 2011

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE\´s Publication Principles.

This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission.

"Using Matlab and Simulink in a SystemC Verification Environment"
Jean-Francois Boland, Claude Thibeault, Zeljko Zilic
In the Proceedings of the Design & Verification Conference (DVCON), 2005

Functional verification is a major part of today\´s system design task. Several approaches are available for verification on a high abstraction level, where designs are often modeled using MATLAB/Simulink. However, different approaches are a barrier to a unified verification flow. In this paper, we propose a co-simulation interface between SystemC and MATLAB and Simulink to enable functional verification of multi-abstraction levels designs. The resulting verification flow is tested on JPEG compression algorithm. The required synchronization of both simulation environments, as well as data type conversion is solved using the proposed co-simulation flow. We divided into two encoder jpeg parts. First implemented in SystemC which is the DCT is representing the party HW. The second consisting of quantization and entropy encoding is implemented in Matlab is the SW part. For communication and synchronization between these two parts we use S-Function and engine in Simulink matlab. With this research premise, this stu- y introduces a new implementation of a Hardware SystemC of DCT. We compare the result of our simulation compared to SW / SW. We observe a reduction in simulation time you have 88.15%.