Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems

A reconfigurable and programmable streaming processor core complemented with interconnected arithmetic units for the acceleration of floating-point operations is presented in this paper. The streaming processor can be easily reconfigured to perform a complex scientific algorithm or computations by changing the set of instructions in a central control unit. By using floating-point arithmetic unit with pipeline streaming data flow, floating-point operations can be performed in each cycle resulting in a high-performance scientific computations. The streaming processor is dedicated for a high-performance adaptive signal processing applications. For higher performance, reliability and fault-tolerance scientific computations, the streaming processor would be designed as a tile processor in a multicore streaming processor system.