Towards a power and energy efficient use of partial dynamic reconfiguration

Nowadays, System-on-Chip architectures are composed of several execution resources which support complex applications. These applications increasingly need flexibility to adapt to their environment. Embed a reconfigurable resource in these SoC enables to flexibilize the hardware by sharing silicon area and limiting the cost of the global circuit. Partial reconfiguration is more and more used since it enables to fully exploit the resource but there is few work in the characterization of the energy consumption during reconfiguration. This paper presents the work on modeling energy using partial dynamic reconfiguration with empty tasks to reduce power consumption and an example on an application.